Verilog HDL syntax error near text "for"; expecting "endmodule" -

so got around learning verilog , implementing basic binary adder in it. limited understanding of verilog, following should add 2 16-bit values.

module add(x, y, z); input[15:0] x; input[15:0] y;  output z[15:0]; wire c[15:0];  assign c[0] = 0; integer i; for(i=1; i<16; i=i+1) begin  assign c[i]=(x[i-1]&y[i-1])|(x[i-1]&c[i-1])|(y[i-1]&c[i-1]); end for(i=0; i<16; i=i+1) begin assign z[i]=x[i]^y[i]^c[i]; end endmodule 

however, error when try synthesize above.

error (10170): verilog hdl syntax error @ add.v(10) near text "for"; expecting "endmodule"

i'm not sure wrong code. appreciated!

the for-loop used outside of block, i needs genvar instead of integer. also, want z , c declared packed arrays instead of unpacked, mo [15:0] other side.

output [15:0] z; // make packed bits wire [15:0] c;  assign c[0] = 0; genvar i; // not integer generate // required ieee 1364-2001, optional *-2005 , systemverilog for(i=1; i<16; i=i+1) begin    assign c[i]=(x[i-1]&y[i-1])|(x[i-1]&c[i-1])|(y[i-1]&c[i-1]); end for(i=0; i<16; i=i+1) begin   assign z[i]=x[i]^y[i]^c[i]; end endgenerate // must matched generate 

alternative solution 1: use block

output reg[15:0] z; // make reg reg [15:0] c;  integer i; // integer ok @* begin   for(i=1; i<16; i=i+1) begin     if (i==0)  c[i] = 1'b0;     else       c[i]=(x[i-1]&y[i-1])|(x[i-1]&c[i-1])|(y[i-1]&c[i-1]);     z[i]=x[i]^y[i]^c[i];   end end 

alternative solution 2: bit-wise assignment

output [15:0] z;  wire [15:0] c = { (x&y)|(x&c)|(y&c) , 1'b0 }; assign z = x^y^c; 

alternative solution 3: behavioral assignment

output [15:0] z; assign z = x+y; 

working examples here