Booth's algorithm Verilog synthesizable -

i trying implement booth's algorithm (a finite state machine implementation) xilinx fpga. basically, @ start signal initialize auxiliary regs, go in state 0, start compare 2 bits , shifting. repeat until state 4 reached.

assign result = p[8:1];  always@(posedge clk or negedge start)     if(start == 1)     begin             // initialize start values         state <= 3'd0;     end      else     if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)     begin        // compare bits , shift data     end endmodule 

test module

clk = 0; = 4'b0011; b = 4'b0011; b = ~b+1; start = 1; #10; start = 0; 

clk becomes ~clk after #5 time units.

i not own fpga, cannot test program (i'll have test later @ class).

i testing icarus. problem auxiliary regs not initialized before first posedge of clock.

what can in order initialize auxiliary variables , maintain code synthesizable? i've tried using loop , initial begin, , simulation works fine, not work on fpga (because have use #delays).

for asic best use active low resets set initial values fpgas common set initial values in initial blocks.

initial begin   state = 'd0 ; end  always@(posedge clk) begin   if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)begin     // compare bits , shift data     state <= 3'd4 ;   end endmodule 

using active low resets.

always@(posedge clk or negedge rst_n) begin   if (~rst_n) begin     state <= 'd0 ;   end    else begin     if(state == 3'd0 || state == 3'd1 || state == 3'd2 || state == 3'd3)begin       // compare bits , shift data       state <= 3'd4 ;     end   end endmodule