matlab - Why is a sum statement so bizarrely synthesized? -


i have 4 buttons on fpga dev board wrote

function [hex0] = bar(key)   n = uint8(sum(key, 'native'));   ...

unfortunately, hdl coder turned following chunk of vhdl:

y := '0';  k in 0 3 loop   y := y or key(k); end loop;  y_0 := '0' & '0' & '0' & '0' & '0' & '0' & '0' & y;

which don't get. can me figure out what's going on here?

to understand this, have understand matlab sum logical inputs , native option. sum of logicals logical. sum replaced or

sum([true,true],'native')

and coder puts out. for-loop implements sum (sum(key, 'native')), coder recognizes implemented using or.

finally, conversion logical uint8 done padding 7 0 bits.


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